1. Field of the Invention
The present invention relates to an image sensing apparatus and an imaging system.
2. Description of the Related Art
According to the technique disclosed in Japanese Patent Laid-Open No. 2001-45378, in a pixel array including a plurality of pixels arrayed in the row and column directions, driving signals are supplied to the pixels via a plurality of row control lines extending in the row direction, and signals are read out from the pixels via a plurality of column signal lines extending in the column direction. An accumulation unit is connected to each end of a column signal line. When a signal is being read out from one of the two accumulation units, a signal output from a pixel is accumulated in the other accumulation unit. This shortens the blanking period (period without sensor output) and the entire readout period for reading out signals from the pixel array to the accumulation units.
In the technique of Japanese Patent Laid-Open No. 11-150255, two accumulation units and two amplifiers are alternately connected to each of a plurality of column signal lines. A signal accumulated in one of the two accumulation units is amplified and output by one of the two amplifiers and then accumulated in the other accumulation unit. The signal accumulated in the other accumulation unit is amplified by the other amplifier and then read out to the output line of the succeeding stage.
In the technique of Japanese Patent Laid-Open No. 2001-45378, signals from the pixels of the first row of the pixel array are accumulated in one accumulation unit, whereas signals from the pixels of the second row are accumulated in the other accumulation unit. The signal transferred from each accumulation unit to the output line of the succeeding stage is multiplied by a gain based on a capacitive division ratio determined by the capacitance value of each accumulation unit and that of the output line. For example, when the accumulation unit has a capacitance value C1, and the output line has a capacitance value C2, the gain is given by C1/(C1+C2). The capacitance value of the output line contains its parasitic capacitance and a capacitance value generated by a capacitive element provided on it. In the readout technique of Japanese Patent Laid-Open No. 2001-45378 using such capacitive division, when the absolute value of the capacitance of each of one and other accumulation units is small, the gain based on the capacitive division ratio between the output line of the succeeding stage and the capacitance of each accumulation unit becomes small, and the S/N ratio lowers. Conversely, when the absolute value of the capacitance of each of one and other accumulation units is large, the gain based on the capacitive division ratio between the output line of the succeeding stage and the capacitance of each accumulation unit becomes large, and the S/N ratio rises. However, this increases the electrode area of each of one and other accumulation units, resulting in an increase in the chip area.
According to the technique of Japanese Patent Laid-Open No. 11-150255, the signal accumulated in the other accumulation unit is amplified by the other amplifier and read out to the succeeding stage, as described above. It is therefore possible to read out the signal to the output line of the succeeding stage without considering the gain based on the capacitive division ratio. However, since two amplifiers are connected, for one signal, to each of the plurality of column signal lines, the chip area of the image sensing apparatus may increase. In addition, since two amplifiers operate for reading out one signal, the entire power consumption in the entire readout period in the image sensing apparatus may increase.